Hi Wolfram, > > dev->status can be used to record the current state, especially Designware > > I2C controller has no interrupts to identify a write-request. This patch > > Just double-checking: the designware HW does not raise an interrupt when > its own address + RW bit has been received? Not exactly. There're an interrupt state name "RD_REQ" but no one named like "WR_REQ". For read-request, the slave will get a RD_REQ interrupt. For write-request, the slave won't be interrupted until data arrived to trigger interrupt "RX_FULL". I tried to use GPIO to simulate an I2C master. I only sent its own address + W bit without any data and then I got only a STOP_DET interrupt. If I sent its own address + W bit + one byte data and then I got one RX_FULL and a STOP_DET. It seems the controller doesn't interrupt when RW bit is W, but R does. What do you think, Jarkko? Sincerely, Michael Wu
