Hi Enrico On 8/8/19 7:17 PM, Enrico Weigelt, metux IT consult wrote: > On 02.08.19 14:51, Jean Delvare wrote: > > Hi, > >> These patches fix a couple of issues with the i2c-piix4 driver on >> AMD Family 16h Model 30h SoCs and add ACPI-based enumeration to the >> i2c-piix4 driver. > Can you tell a little bit more about what devices are behind the smbus ? > I recall the G-412 SoCs (such as on apu2+ boards) have an Hudson inside > and fall into this category. (I'll have to check when back in office), > so (as the apu2 platform driver maintainer) I'm very interested in this. My initial work is based on a board that is similar to the APU2, but has additional peripherals connected to the smbus, including a NCT7491 thermal monitor/fan controller and PCA6524 GPIO controller. These are simply peripherals on a board variant, not 'platform' devices, so I didn't want to follow the platform driver approach that the APU2 GPIO driver uses. > > Does the probing need some special BIOS support (or do the necessary > table entries already come from aegesa) ? SMBus (and I2C) peripherals can generally not be enumerated without some firmware support. It is possible to probe for specific devices on the bus (eg sensors-detect) but in general it is not feasible to let every supported device driver probe the bus for its device. ACPI and Devicetree provides the kernel with metadata for the device: type, address, calibrated set points for temperature, etc. Since the peripherals are not standard platform devices, they are not described by the ACPI tables provided by Coreboot or AMD, but it's not too difficult to create supplementary device description tables (ACPI) for non-standard devices. These can be added to coreboot, supplied to qemu as additional firmware files (see -acpitable arg), or built into the kernel (see https://www.kernel.org/doc/Documentation/acpi/ssdt-overlays.txt) ACPI may be an ugly abomination, but it's what we're stuck with on x86 and it can only improve when more people get their hands on it. > > I have to admit, I'm still confused by the AMD documentation - haven't > found a clear documentation on what peripherals exactly are in the > G-412 SoC, just puzzled together that the FCH seems to be an Hudson, > probably v2. There also seems to be some relation between smbus and > gpio, but the gpio's are directly memory-mapped - no idea whether they > just share the same base address register or the gpios are really behind > smbus and some hw logic directy maps them into mmio space ... > Do you happen to have some more information on that ? You might find it helpful to look at the coreboot source for the APU2 (src/mainboard/pcengines/apu2/gpio_ftns.h) > > By the way: I'm considering collecting some hw documentation in the > kernel tree (maybe Documentation/hardware/...) - do you folks think > that's a good idea ? Would it be awesome if specs were available for every device supported by the kernel? Absolutely, what a dream! Perhaps a separate repo, like the linux-firmware repo, would be better for binary objects that don't change. Unfortunately, copyright makes this hard. NDAs make this hard. Hardware companies just don't seem to work like that. > > --mtx Regards, Andrew
