Hi, I started to look at i2c multi master mode and I wanted to ask question how HW/PCB should be design to support multi master mode with i2c muxes properly. I found at https://i2c.info/i2c-bus-specification PCA9541 usage as HW solution for multi master coming from two different HW. I have also seen driver in the kernel for it based i2c mux infrastructure. There is also GPIO based arbirtrator driver in the kernel maintain by Peter. I expect that this HW chip of gpio based solution works properly for two external masters. And I have a question if you are aware about any solution done purely based on SW. The reason why I am asking is that on Xilinx boards there are 2 ways how to get the the same I2C bus without any PCA9541 hw based solution and expectation from HW guys is to synchronize master via SW. It means one master can be Linux running on a53 and second RTOS running on R5 inside the same chip. Is there any SW synchronization in place which could be use? Is there any i2c based hw/sw mutex/spinlock chip which should be used instead of HW PCA9541 solution? (on zcu102 there could be even 3 masters). Thanks, Michal
