Hi, Yes Jarkko. Registers are on the PCLK domain (applications clock) and the IC_CLK is the clock that controls peripheral logic (like SCL definition). Thanks! On 26-Feb-19 14:54, Jarkko Nikula wrote: > Hi > > + Luis from Synopsys. > > Sorry the delay, I was out of office last week. Comment below. > > On 2/21/19 6:10 PM, Gareth Williams wrote: >> From: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> >> >> The driver requires an undocumented clock property, so detail it. >> Add documentation for a separate, optional, peripheral clock. >> >> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> >> Acked-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> >> --- >> v4: >> - Updated commit message to reference "peripheral clock" instead of >> "bus clock" >> - Added Wolfram's Acked-by >> v3: >> - Changed clocks and clock-names sections to use term "peripheral clock" >> (pclk) instead of "bus clock" (busclk). > ... >> Optional properties : >> + >> + - clock-names : Contains the names of the clocks: >> + "ic_clk", for the core clock used to generate the external I2C clock. >> + "pclk", the peripheral clock, required for register accesses. >> + > > Actually it looks there is need to revert back to bus clock (or better) in > comments but keep the "pclk" property. > > The specification I have tells the ic_clk is the peripheral clock which runs the > logic and the pclk (exactly pclk) is for bus interface and where registers are. > > Luis: did I interpret it right? >
