On Wed, Jan 30, 2019 at 10:16:27PM -0800, Sowjanya Komatineni wrote: > This patch adds I2C interface timing registers support for > proper bus rate configuration along with meeting the i2c spec > setup and hold times based on the tuning performed on Tegra210, > Tegra186 and Tegra194 platforms. > > I2C_INTERFACE_TIMING_0 register contains TLOW and THIGH field > and Tegra I2C controller design uses them as a part of internal > clock divisor. > > I2C_INTERFACE_TIMING_1 register contains the setup and hold times > for start and stop conditions. > > Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx> > --- > [V8] : Updated to handle timing implementation within tegra_i2c_init directly > [V7] : Minor updates to timing implementation > [V5/V6] : Added this Interface timing patch in V5 of the patch series. > > drivers/i2c/busses/i2c-tegra.c | 187 ++++++++++++++++++++++++++++++++++------- > 1 file changed, 158 insertions(+), 29 deletions(-) Acked-by: Thierry Reding <treding@xxxxxxxxxx>
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