This reverts commit fba4adbbf670577e605f9ad306629db6031cd48b. Not all revisions of DW I2C controller implement the enable status register. On platforms where that's the case (e.g. BG2CD and SPEAr ARM SoCs), waiting for enable will time out as reading the unimplemented register yields zero. As documentation implies that polling DW_IC_ENABLE_STATUS is not required when enabling the adapter, it's plausible that the problem is elsewhere. If this reintroduces the problem observed by Ben in spite of IRQ disabling added in the previous patch, and if no better fix is found, then waiting for enable should check DW_IC_COMP_VERSION to avoid regressions. Cc: Ben Gardner <gardner.ben@xxxxxxxxx> Cc: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx> Cc: Wolfram Sang <wsa@xxxxxxxxxxxxx> Signed-off-by: Alexander Monakov <amonakov@xxxxxxxxx> --- drivers/i2c/busses/i2c-designware-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c index e7fd0e57ab1f..a80926d86a29 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -210,7 +210,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) i2c_dw_disable_int(dev); /* Enable the adapter */ - __i2c_dw_enable_and_wait(dev, true); + __i2c_dw_enable(dev, true); /* Clear and enable interrupts */ dw_readl(dev, DW_IC_CLR_INTR); -- 2.11.0
