Hi Wolf,
For the upcoming AMD platform we have new i2c hardware design in place as shown below.
+----------------------------------------------------------+
| |
| +---------------------+ +---------------------+ |
+--------> | I2C Host Driver | | GPIO Controller <-------------+
| | +----------+----------+ +---------------------+ | |
| | | | |
| | | | |
| | +-----------------------+ | |
| | | PCI Driver interface| | |
| | +-------------^---------+ x86 Domain | |
| | | | |
| | | | |
| | | | |
| +----------------------------------------------------------+ |
| | |
| |C2P/P2C mailbox |
| | Interrupt |
+---v------+ | |
| DRAM | | |
| | +-------+---------------------------+ +--------------+---+
+--- ^-----+ | | | |
| | +-----------+ +-------------+ | + I2C Slave |
| | I2C FW <---->I2C engine <-----> |
| DATA | +-----^-----+ +-----+-------+ | +------------------+
|Read/Write | | | |
| | +----------------+ |
+-------------->+ MP2 Domain |
+-----------------------------------+
X86 Host controller does not have actual I2C controller. The Actual I2C controller is with MP2 ( ARM Processor) interfaced with x86. The communication between X86 Host controller and Mp2 can happen via PCI Interface.
The MP2 runs I2C firmware and there is a set of protocol defined between Mp2 and X86 to do any I2C transactions. There are register banks between I2C and MP2 called as C2P and P2C. For any I2C command to be sent from X86 to MP2,
this C2P and P2C mailbox is used. For the r/w data path, there are two path flow. If data is less than 32 bytes, it can be still accessed viqa P2C/C2P mailbox. If data is more than 32 bytes, then there is a common DRAM between
X86 and MP2 through the other interface.
Now we have developed two new drivers.
1. I2C host controller bus driver: This is based on I2C framework of linux kernel. So any i2c read write call or commands to this driver is routed to PCI Interface driver.
2. PCI Driver : This driver is responsible to talk with Mp2 and does all C2P/P2C communication or reading/writing from DRAM in case of more data.
How can we get this driver to be upstreamed? Is it fine to put this driver at drivers/i2c/busses and submit the patches. Please provide your valuable inputs.
Thanks and Regards
Nehal Shah
