Hi Jarkko, On Tue, 11 Oct 2016 14:32:55 +0300, Jarkko Nikula wrote: > On 10/11/2016 02:13 PM, Jean Delvare wrote: > > Starting with the 8-Series/C220 PCH (Lynx Point), the SMBus > > controller includes a SPD EEPROM protection mechanism. Once the SPD > > Write Disable bit is set, only reads are allowed to slave addresses > > 0x50-0x57. > > > > However the legacy implementation of I2C Block Read since the ICH5 > > looks like a write, and is therefore blocked by the SPD protection > > mechanism. This causes the eeprom and at24 drivers to fail. > > > > So assume that I2C Block Read is implemented as an actual read on > > these chipsets. I tested it on my Q87 chipset and it seems to work > > just fine. > > > > Signed-off-by: Jean Delvare <jdelvare@xxxxxxx> > > Cc: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx> > > Cc: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> > > Cc: Wolfram Sang <wsa@xxxxxxxxxxxxx> > > --- > > Changes since v1: > > * Rebased on Linus' latest tree. > > > > Jarkko, still no information about this from your Windows or hardware > > folks? > > No update, in fact some of the contacts have left the company :-( What do we do then? Without this patch, I2C Block Read doesn't work at all on recent chipsets. I don't think it can be worse with the patch. And it works fine on the few machines I tested on. So I would like this patch to go upstream. My coverage is limited though. Did anyone at Intel test this patch on other (recent) systems? -- Jean Delvare SUSE L3 Support -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
