On Wed, Nov 18, 2015 at 3:31 PM, Lars-Peter Clausen <lars@xxxxxxxxxx> wrote:
> On 11/17/2015 03:28 PM, Shubhrajyoti Datta wrote:
>> On Tue, Nov 17, 2015 at 1:04 PM, Lars-Peter Clausen <lars@xxxxxxxxxx> wrote:
>>> On 11/17/2015 06:17 AM, Shubhrajyoti Datta wrote:
>>>> On Mon, Nov 16, 2015 at 7:12 PM, Lars-Peter Clausen <lars@xxxxxxxxxx> wrote:
>>>>> Commit d701667bb331 ("i2c: xiic: Do not reset controller before every
>>>>> transfer") removed the reinitialization of the controller before the start
>>>>> of each transfer. Apparently this change is not safe to make and the commit
>>>>> results in random I2C bus failures.
>>>>
>>>> Which is the platform and the ip version that you saw the issue.
>>>> Did you see the issue with read and write as well?
>>>
>>> The IP version is the axi-iic v2.0 Revision 8. I've tested this on a few
>>> platforms, custom ones and standard ones and I could reproduce it on most.
>>> One of them was on the ZED board. The one where I couldn't reproduce it was
>>> the ZC706. But that doesn't necessarily mean it doesn't happen there, just
>>> that it is not triggered by the testcase.
>> All the boards having the same version of the ip is what I have understood.
>>
>> Thanks for the info I will try to reproduce the issue.
>>
>>>
>>> The problem is that it is random corruption,
>> Of registers?
>
> To be honest I don't know if there is corruption during I2C write transfers,
> but there is definitely corruption during read transactions.
Ok
Actually I was thinking it is only an issue with
<quote>
/* dynamic mode seem to suffer from problems if we just flushes
* fifos and the next message is a TX with len 0 (only addr)
* reset the IP instead of just flush fifos
*/
xiic_reinit(i2c);
<\quote>
I think as of now since read is also impacted we can revert it.
> - Lars
>
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