On Wed, Sep 09, 2015 at 10:30:32AM +0000, Barry Song wrote:
> From: Guoying Zhang <Guoying.Zhang@xxxxxxx>
>
> In prima2 and atlas7, due to some hardware design issue. we
> need to adjust the divider ratio a little according to i2c
> bus frequency ranges.
> Since i2c is open drain interface that allows the slave to
> stall the transaction by holding the SCL line at '0', the RTL
> implementation is waiting for SCL feedback from the pin after
> setting it to High-Z ('1'). This wait adds to the high-time
> interval counter few cycles of the input synchronization
> (depending on the SCL_FILTER_REG field), and also the time it
> takes for the board pull-up resistor to rise the SCL line.
> For slow SCL settings these additions are negligible, but they
> start to affect the speed when clock is set to faster frequencies.
> This patch is based on the actual tests, and it makes SCL more
> accurate.
>
> Signed-off-by: Guoying Zhang <Guoying.Zhang@xxxxxxx>
> Signed-off-by: Barry Song <Baohua.Song@xxxxxxx>
Applied to for-next, thanks!
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