Re: [PATCH v2] i2c: davinci: Optimize clock generation on Keystone SoC

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On Mon, Sep 14, 2015 at 11:03:50AM +0200, Alexander Sverdlin wrote:
> According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed
> additive part of frequency divisors (referred as "d" in the code and datasheet)
> always equals to 6, independent of module clock prescaler.
> 
>                          module clock frequency

Applied to for-next, thanks!

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