> I asked Kataoka-san about this and his response was as follows: Thanks, Simon! > If system(CPU) is busy, the driver can't clear the status register soon > after kicking start. > > If sequence of first start is as follows, there is a problem. > Because H/W starts by 1. > But sequence of re-start is as follows, there is no problem. > Because H/W starts by 2. > > 1. Issue START condition by ESG bit of ICMCR register. > <--- If there is too much time, H/W finish transmitting > and set status in status register. > 2. Clear interrupt status (ICMSR). > 3. Open interrupt mask. > 4. Wait interrupt. > <--- If status is cleared, interrupt does not occur. I understand. I'll add this explanation to the patch and apply it soon.
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