On Thu, Dec 11, 2014 at 07:02:40PM +0800, Addy Ke wrote: > The number of clock cycles to be written into the CLKDIV register > that determines the I2C clk high phase includes the rise time. > So to meet the timing requirements defined in the I2C specification > which defines the minimal time SCL has to be high, the rise time > has to taken into account. The same applies to the low phase with > falling time. > > In my test on RK3288-Pink2 board, which is not an upstream board yet, > if external pull-up resistor is 4.7K, rise_ns is about 700ns. > So the measured high_ns is about 3900ns, which is less than 4000ns > (the minimum high_ns in I2C specification for Standard-mode). > > To fix this bug min_low_ns should include fall time and min_high_ns > should include rise time. > > This patch merged the patch from chromium project which can get the > rise and fall times for signals from the device tree. This allows us > to more accurately calculate timings. see: > https://chromium-review.googlesource.com/#/c/232774/ > > Signed-off-by: Addy Ke <addy.ke@xxxxxxxxxxxxxx> Applied to for-next, thanks! I fixed the typo Doug mentioned. Please send new patches as seperate threads, not as a reply to the old patch.
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