Hi all,
There were "i2c_designware 80860F41:00: controller timed out" errors
on a number of Baytrail platforms. They typically occurred during suspend
resume where some short i2c transfers were exchanged with devices. And they
mostly occurred when using fast mode, not standard mode.
The cause of the problem is that interrupts start right away when the
controller is enabled. There's this comment in __i2c_dw_enable:
/*
* Wait 10 times the signaling period of the highest I2C
* transfer supported by the driver (for 400KHz this is
* 25us) as described in the DesignWare I2C databook.
*/
The __i2c_dw_enable then does a usleep for 25us to 250us, but since interrupts
were previously enabled, this wait wasn't being respected by ISR. With
additional traces, we could see ISR was activated and finished i2c transfer
while the code was still inside __i2c_dw_enable. At combination of fast
mode, certain transfer size and device response time, i2c_dw_clear_int was executed
and cleared STOP condition flag, which resulted in i2c time out.
static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
{
...
/* Enable the adapter */
__i2c_dw_enable(dev, true);
/* Clear and enable interrupts */
i2c_dw_clear_int(dev);
dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
}
The patch disables interrupts before the controller is enabled to remove this
race condition.
Signed-off-by: Wenkai Du <wenkai.du@xxxxxxxxx>
---
drivers/i2c/busses/i2c-designware-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index 14c4b30..71a3fa9 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -417,6 +417,9 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
*/
dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
+ /* disable interrupts */
+ i2c_dw_disable_int(dev);
+
/* Enable the adapter */
__i2c_dw_enable(dev, true);
--
1.7.9.5
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