Re: [PATCH] i2c: mxs: fix broken timing calculation

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Hi,

Marek Vasut writes:
> Hi Lothar,
> 
> > The timing calculation is rather bogus and gives extremely wrong
> > results for higher frequencies (on an i.MX28). E.g. instead of 400 kHz
> > I measured 770 kHz.
> > 
> > Implement a calculation that adheres to the I2C spec and gives exact
> > results for I2C frequencies from 12.56 kHz to 960 kHz.
> > 
> > Also the bus_free and leadin parameters are programmed according to
> > the I2C spec for standard and fast mode.
> 
> I suspect the resulting speed is heavily dependent on hardware properties of the 
> bus. Did you have a chance to check it with a scope? I will try to recheck on 
> other boards next week.
> 
Of course I did! I found the DS1339 RTC not working on our hardware
with the I2C clock frequency set to 400kHz and then checked the bus
timing. I found the SCL frequency to be 770kHz instead of 400kHz and
113kHz instead of 100kHz.
On what hardware did you do your measurements?

The fancy constants -2 and -7 in the calculation were derived from
measuring the clock low and high time with low_count and high_count
set to 1 and measuring the actual timing of the signal.
The clock frequeny in this setup is 2.18 MHz corresponding to 11 clock
cycles of the 24MHz clock. The LOW time was about 140ns and the HIGH
time 318ns corresponding to 3 and 8 (instead of 1) clock cycles.

These constants could be different for different SoCs (i.MX23).
But I don't have any hardware to verify that.

Maybe some guru from Freescale can comment on this and perhaps
document the relationship between the register contents and the actual
timing.



Lothar Waßmann
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