Hi all,
I added just a few lines to the documentation file, the code part of the patch
in unchanged.
Signed-off-by: Rudolf Marek <r.marek@xxxxxxxxxxxx>
Attached patch adds support for secondary SMBus of AMD SB800 and new AMD FCH
Hudson chipsets. The base address of secondary SMBus is different from SB700 and
it is stored on similar place as SB800 primary SMBus.
Thanks
Rudolf
Index: linux-3.10-rc6/drivers/i2c/busses/i2c-piix4.c
===================================================================
--- linux-3.10-rc6.orig/drivers/i2c/busses/i2c-piix4.c 2013-06-15 23:51:07.000000000 +0200
+++ linux-3.10-rc6/drivers/i2c/busses/i2c-piix4.c 2013-06-17 23:30:48.198871798 +0200
@@ -231,11 +231,11 @@
}
static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
- const struct pci_device_id *id)
+ const struct pci_device_id *id, u8 aux)
{
unsigned short piix4_smba;
unsigned short smba_idx = 0xcd6;
- u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;
+ u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en;
/* SB800 and later SMBus does not support forcing address */
if (force || force_addr) {
@@ -245,6 +245,8 @@
}
/* Determine the address of the SMBus areas */
+ smb_en = (aux) ? 0x28 : 0x2c;
+
if (!request_region(smba_idx, 2, "smba_idx")) {
dev_err(&PIIX4_dev->dev, "SMBus base address index region "
"0x%x already in use!\n", smba_idx);
@@ -272,6 +274,13 @@
return -EBUSY;
}
+ /* Aux SMBus does not support IRQ information */
+ if (aux) {
+ dev_info(&PIIX4_dev->dev,
+ "SMBus Host Controller at 0x%x\n", piix4_smba);
+ return piix4_smba;
+ }
+
/* Request the SMBus I2C bus config region */
if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
@@ -596,7 +605,7 @@
dev->revision >= 0x40) ||
dev->vendor == PCI_VENDOR_ID_AMD)
/* base address location etc changed in SB800 */
- retval = piix4_setup_sb800(dev, id);
+ retval = piix4_setup_sb800(dev, id, 0);
else
retval = piix4_setup(dev, id);
@@ -610,17 +619,29 @@
return retval;
/* Check for auxiliary SMBus on some AMD chipsets */
+ retval = -ENODEV;
+
if (dev->vendor == PCI_VENDOR_ID_ATI &&
- dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
- dev->revision < 0x40) {
- retval = piix4_setup_aux(dev, id, 0x58);
- if (retval > 0) {
- /* Try to add the aux adapter if it exists,
- * piix4_add_adapter will clean up if this fails */
- piix4_add_adapter(dev, retval, &piix4_aux_adapter);
+ dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
+ if (dev->revision < 0x40) {
+ retval = piix4_setup_aux(dev, id, 0x58);
+ } else {
+ /* SB800 added aux bus too */
+ retval = piix4_setup_sb800(dev, id, 1);
}
}
+ if (dev->vendor == PCI_VENDOR_ID_AMD &&
+ dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
+ retval = piix4_setup_sb800(dev, id, 1);
+ }
+
+ if (retval > 0) {
+ /* Try to add the aux adapter if it exists,
+ * piix4_add_adapter will clean up if this fails */
+ piix4_add_adapter(dev, retval, &piix4_aux_adapter);
+ }
+
return 0;
}
Index: linux-3.10-rc6/Documentation/i2c/busses/i2c-piix4
===================================================================
--- linux-3.10-rc6.orig/Documentation/i2c/busses/i2c-piix4 2013-06-15 23:51:07.000000000 +0200
+++ linux-3.10-rc6/Documentation/i2c/busses/i2c-piix4 2013-06-17 23:33:23.024925371 +0200
@@ -73,9 +73,10 @@
The ServerWorks Southbridges, the Intel 440MX, and the Victory66 are
identical to the PIIX4 in I2C/SMBus support.
-The AMD SB700 and SP5100 chipsets implement two PIIX4-compatible SMBus
-controllers. If your BIOS initializes the secondary controller, it will
-be detected by this driver as an "Auxiliary SMBus Host Controller".
+The AMD SB700, SB800, SP5100 and Hudson-2 chipsets implement two
+PIIX4-compatible SMBus controllers. If your BIOS initializes the
+secondary controller, it will be detected by this driver as
+an "Auxiliary SMBus Host Controller".
If you own Force CPCI735 motherboard or other OSB4 based systems you may need
to change the SMBus Interrupt Select register so the SMBus controller uses
