On Tue, May 28, 2013 at 06:41:09PM +0800, Sonic Zhang wrote: > From: Sonic Zhang <sonic.zhang@xxxxxxxxxx> > > Reported-by: Bob Maris <mail@xxxxxxxxxxx> > > TWI transfer interrupts may be lost when system is heavily handling other > interrupts, while current transfer handler depends on each accurate interrupt > and misses some data in this case. Because there are 2 2-byte FIFOs in blackfin > TWI controller, the occurrence of the data loss can be reduced by reading till > the RX FIFO is empty and writing till the TX FIFO is full. > > Signed-off-by: Sonic Zhang <sonic.zhang@xxxxxxxxxx> Applied to for-next, thanks!
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