On Mon, Apr 15, 2013 at 12:16:54PM +0200, Lucas Stach wrote: > This commit fixes the three following races in PIO code: > > - The CTRL0 register is racy in itself, when programming transfer state and > run bit in the same cycle the hardware sometimes ends up using the state > from the last transfer. Fix this by programming state in one cycle, make > sure the write is flushed down APBX bus by reading back the reg and only > then trigger the run bit. > > - Only clear the DMAREQ bit in DEBUG0 after the read/write to the data reg > happened. Otherwise we are racing with the hardware about who touches > the data reg first. > > - When checking for completion of a transfer it's not sufficient to check > if the data engine finished, but also a check for i2c bus idle is needed. > In PIO mode we are really fast to program the next transfer after a finished > one, so the controller possibly tries to start a new transfer while the > clkgen engine is still busy writing the NAK/STOP from the last transfer to > the bus. > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> Applied to for-next, thanks! Both. I'd prefer to not use reply-to <old_series> when sending <new_series>. -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
