This set of patches enables the Intel PCH SMBus controller interrupt.
The Interrupt can signify:
INTR - the end of a complete transaction
DEV_ERR - that a device did not ACK a transaction
BYTE_DONE - the completion of a single byte during a byte-by-byte transaction
This patchset arrives with the following caveats:
1) It has only been tested with a Cougar Point (Intel 6 Series PCH) SMBus
controller, so the irq is only enabled for that chip type.
2) It has not been tested with any devices that do transactions that use the
PEC. In fact, I believe that an additional small patch would be required
to the driver working correctly in interrupt mode with PEC.
3) It has not been tested in SMBus Slave mode.
4) It has not been tested with SMI#-type interrupts.
5) The BIOS has to configure the PCH SMBus IRQ properly.
6) It has not been tested with a device that does byte-by-byte smbus (non-i2c)
reads.
7) It has not been tested with smbus 'process call' transactions.
If would be very helpful if somebody could help test on other chipsets, with
a PEC device, or on additional BIOS that woudl be very helpful.
In the meantime, the interrupt behavior is only enabled on the Cougar Point,
and even here, it can be completely disabled with the "Interrupt" feature like
other advanced features of the driver.
Daniel Kurtz (3):
i2c: i801: refactor i801_block_transaction_byte_by_byte
i2c: i801: enable irq for i801 smbus transactions
i2c: i801: enable irq for byte_by_byte transactions
drivers/i2c/busses/i2c-i801.c | 193 ++++++++++++++++++++++++++++++++++++-----
1 files changed, 170 insertions(+), 23 deletions(-)
--
1.7.3.1
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