[PATCH v2] OMAP: I2C: Fix the interrupt clearing in OMAP4

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For OMAP4 Interrupt enable register is a legacy register.
To clear the interrupts we were writing 0 to it. However on OMAP4
we were writing 1 to  IRQENABLE_CLR which clears only the arbitration
lost interrupt. The patch intends to fix the same by writing 1
to all the bits.

Signed-off-by: Shubhrajyoti D <shubhrajyoti@xxxxxx>
---
 drivers/i2c/busses/i2c-omap.c |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2dfb631..bf4376f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -167,6 +167,10 @@ enum {
 #define SYSC_IDLEMODE_SMART		0x2
 #define SYSC_CLOCKACTIVITY_FCLK		0x2
 
+
+/* Mask to clear all the interrupts */
+#define OMAP_I2C_IRQENABLE_CLR_ALL	0x6FFF
+
 /* Errata definitions */
 #define I2C_OMAP_ERRATA_I207		(1 << 0)
 #define I2C_OMAP3_1P153			(1 << 1)
@@ -308,8 +312,17 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
 	pdata = pdev->dev.platform_data;
 
 	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+
+	/*
+	 * The Interrupt enable register is a legacy register for OMAP4.
+	 * However to clear all the interrupts we could write 0 to Interrupt
+	 * enable reg  or  should write 1 to all the bits of the
+	 * I2C_IRQENABLE_CLR register.
+	 */
+
 	if (dev->rev >= OMAP_I2C_REV_ON_4430)
-		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
+		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR,
+					OMAP_I2C_IRQENABLE_CLR_ALL);
 	else
 		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 
-- 
1.7.1

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