I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg@xxxxxxxxxxxxxxx>
---
drivers/i2c/busses/Kconfig | 8 +
drivers/i2c/busses/Makefile | 3 +
drivers/i2c/busses/i2c-pch.c | 1390 ++++++++++++++++++++++++++++++++++++++++++
drivers/i2c/busses/i2c-pch.h | 147 +++++
drivers/i2c/i2c-dev.c | 28 +
5 files changed, 1576 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
create mode 100644 drivers/i2c/busses/i2c-pch.h
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..578fd42 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -7,6 +7,14 @@ menu "I2C Hardware Bus support"
comment "PC SMBus host controller drivers"
depends on PCI
+config PCH_I2C
+ tristate "PCH I2C"
+ depends on PCI
+ help
+ This driver is for PCH I2C of Topcliff which is an IOH for x86
+ embedded processor.
+ This driver can access PCH I2C bus device.
+
config I2C_ALI1535
tristate "ALI 1535"
depends on PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..53be4b3 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -78,3 +78,6 @@ obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
EXTRA_CFLAGS += -DDEBUG
endif
+
+obj-$(CONFIG_PCH_I2C) += pch_i2c.o
+pch_i2c-objs := i2c-pch.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..58824cc
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,1390 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+
+#include "i2c-pch.h"
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static s32(*pch_cbr) (struct i2c_algo_pch_data *);
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ iowrite32(((ioread32(addr + offset)) | (bitmask)), (addr + offset));
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ iowrite32(((ioread32(addr + offset)) & (~(bitmask))), (addr + offset));
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "Cleared the registers PCH_I2CCTL,PCH_I2CMOD,PCH_I2CBUFFOR\n,"
+ "PCH_I2CBUFSLV,PCH_I2CBUFSUB,PCH_I2CBUFMSK,\n"
+ "PCH_I2CESRFOR,PCH_I2CESRMSK\n");
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ __func__, ioread32(p + PCH_I2CCTL),
+ pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* get the status of bus busy */
+ reg_value = (ioread32(p + PCH_I2CSR) & I2CMBB_BIT);
+
+ while ((timeout != 0) && (reg_value != 0)) {
+ msleep(1); /* wait for 100 ms */
+ reg_value = ioread32(p + PCH_I2CSR) & I2CMBB_BIT;
+
+ timeout--;
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ dev_err(adap->pch_adapter.dev.parent,
+ "%s :return%d\n", __func__, -ETIME);
+ } else {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : return %d\n", __func__, 0);
+ }
+
+ return ((timeout <= 0) ? (-ETIME) : (0));
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "Invoke %s successfully. I2CCTL = %x\n", __func__, PCH_I2CCTL);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ u32 temp_flag;
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s adap->pch_event_flag = %x", __func__, adap->pch_event_flag);
+ temp_flag = adap->pch_event_flag;
+ adap->pch_event_flag = 0;
+
+ if (ret == 0) {
+ dev_err(adap->pch_adapter.dev.parent,
+ "%s : Timeout\n", __func__);
+ } else if (ret < 0) {
+ dev_err(adap->pch_adapter.dev.parent,
+ "%s failed : Interrupted by other signal\n", __func__);
+ ret = -ERESTARTSYS;
+ } else if ((temp_flag & I2C_ERROR_MASK) == 0) {
+ ret = 0;
+ } else {
+ dev_err(adap->pch_adapter.dev.parent,
+ "%s failed : Error in transfer\n", __func__);
+ }
+
+ dev_err(adap->pch_adapter.dev.parent, "%s returns %d\n", __func__, ret);
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val == 0)
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : return 0\n",
+ __func__);
+ else
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : return%d\n",
+ __func__, -EPROTO);
+
+ return (((reg_val) == 0) ? (0) : (-EPROTO));
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_REPSTART);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : I2CCTL = %x msgs->len = %d\n", __func__,
+ ioread32(p + PCH_I2CCTL), length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : writing %x to Data register\n",
+ __func__, buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ wrcount = -ETIME;
+ break;
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return %d", __func__, 0);
+
+ if (pch_getack(adap)) {
+ wrcount = -ETIME;
+ break;
+ }
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ }
+
+ dev_err(adap->pch_adapter.dev.parent,
+ "%s return=%d\n", __func__, wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "Invoke %s successfully. I2CCTL = %x\n", __func__, PCH_I2CCTL);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0)
+ && (pch_getack(adap) == 0)) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return %d", __func__, 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] =
+ ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_buff_mode_start() - Generate I2C start condition in buffer mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_buff_mode_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CBUFCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CBUFCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CBUFCTL,
+ PCH_BUFF_START);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CBUFCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CBUFCTL));
+}
+
+/**
+ * pch_eeprom_swrst_start() - Generate I2C start condition in EEPROM sw reset
+ * mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_eeprom_swrst_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CESRCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CESRCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CESRCTL,
+ PCH_ESR_START);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "Invoked %s successfully. I2CESRCTL = %x\n", __func__,
+ PCH_I2CESRCTL);
+}
+
+/**
+ * pch_entcb() - Function to register call back function
+ * @pch_ptr: Pointer to call back function.
+ */
+static void pch_entcb(s32(*pch_ptr) (struct i2c_algo_pch_data *adap))
+{
+ if (pch_ptr != NULL) {
+ /* set the handler call back function */
+ pch_cbr = pch_ptr;
+ }
+}
+
+/**
+ * pch_handler() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler(int irq, void *pData)
+{
+ s32 ret;
+ u32 i;
+
+ struct adapter_info *adap_info = (struct adapter_info *)pData;
+ /* invoke the call back */
+
+ if (pch_cbr != NULL) {
+ for (i = 0, ret = 0; i < PCH_MAX_CHN; i++)
+ ret |= (pch_cbr) (&adap_info->pch_data[i]);
+ } else {
+ dev_err(adap_info->pch_data[0].pch_adapter.dev.parent,
+ "%s Call back pointer null ...", __func__);
+ return IRQ_NONE;
+ }
+
+ dev_dbg(adap_info->pch_data[0].pch_adapter.dev.parent,
+ "%s return = %d\n", __func__, ret);
+
+ if (ret == PCH_EVENT_SET)
+ dev_dbg(adap_info->pch_data[0].pch_adapter.dev.parent,
+ "%s return IRQ_HANDLED", __func__);
+ else
+ dev_dbg(adap_info->pch_data[0].pch_adapter.dev.parent,
+ "%s return IRQ_NONE", __func__);
+
+ return (ret == PCH_EVENT_SET) ? (IRQ_HANDLED) : (IRQ_NONE);
+}
+
+/**
+ * pch_buffer_read() - Function to read data from I2C bus in buffer mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ */
+static s32 pch_buffer_read(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u32 loop;
+ u32 rdcount;
+ u32 length;
+ u32 i2cbufsub;
+ u32 addr;
+ u32 i2cbufslv_7_lsb;
+ u32 i2cbufslv_10_9_bit;
+ u32 msglen;
+ void __iomem *p = adap->pch_base_address;
+ /* initialize to invalid length, so that no sub address is tx-ed */
+ u32 subaddrlen = 5;
+ u32 i2cmod_prev;
+ s32 i;
+ u32 time_interval = i2c_adap->timeout;
+ u32 i2ctmr;
+ s32 retvalue;
+ u8 *buf;
+
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ iowrite32(BUFFER_MODE_INTR_ENBL, p + PCH_I2CBUFMSK);
+ /* get the current value of I2C mod register */
+ i2cmod_prev = ioread32(p + PCH_I2CMOD);
+
+ /* enable buffer mode */
+ iowrite32(PCH_BUFFER_MODE, p + PCH_I2CMOD);
+ if (time_interval > 10)
+ time_interval = 10;
+
+ /* value of I2CT = (Timeout interval * PCLK frequency)/ 8 */
+ i2ctmr = (time_interval * (pch_clk)) / 8;
+
+ iowrite32(i2ctmr, p + PCH_I2CTMR);
+ /* if 10 bit addressing is selected */
+
+ if (msgs->flags & I2C_M_TEN) {
+ /* get the 8 LSBits */
+ i2cbufslv_7_lsb = (addr & I2C_ADDR_MSK);
+
+ /* get the 2 MSBits */
+ i2cbufslv_10_9_bit = ((addr & I2C_MSB_2B_MSK) << 1);
+
+ iowrite32(TEN_BIT_ADDR_DEFAULT | i2cbufslv_7_lsb |
+ i2cbufslv_10_9_bit, p + PCH_I2CBUFSLV);
+ } else {
+ iowrite32((addr & I2C_ADDR_MSK) << 1, p + PCH_I2CBUFSLV);
+ }
+
+ /* get sub address length, restrict to 4 bytes max */
+ subaddrlen =
+ (buf[0] <= SUB_ADDR_LEN_MAX) ? (buf[0]) : (SUB_ADDR_LEN_MAX);
+
+ for (i = (subaddrlen - 1), i2cbufsub = 0; i >= 0; i--) {
+ /* frame the sub address based on the length */
+ i2cbufsub |= (((u32) buf[2 - i]) << (8 * i));
+ }
+
+ msglen = length - (subaddrlen + 1);
+
+ loop = subaddrlen + 1;
+
+ /* write the sub address to the reg */
+ iowrite32(i2cbufsub, p + PCH_I2CBUFSUB);
+ /* clear buffers */
+ iowrite32(CLR_REG, p + PCH_I2CBUFLEV);
+
+ rdcount = (msglen <= BUF_LEN_MAX) ? (msglen) : (BUF_LEN_MAX);
+
+ iowrite32((rdcount << 4) | PCH_BUF_RD | subaddrlen, p + PCH_I2CBUFFOR);
+
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) {
+ retvalue = -ETIME;
+ goto return_err;
+ }
+
+ pch_buff_mode_start(adap);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "buffer mode start\n");
+
+ if ((ioread32(p + PCH_I2CBUFSTA) & I2CBMDZ_BIT) != 0) {
+ dev_err(adap->pch_adapter.dev.parent, "buffer read error 1\n");
+ retvalue = -EIO;
+ goto return_err;
+ }
+
+ if (pch_wait_for_xfer_complete(adap) == -ETIME) {
+ dev_err(adap->pch_adapter.dev.parent, "buffer read error2\n");
+ retvalue = -EIO;
+ goto return_err;
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "pch_wait_for_xfer_complete return 0\n");
+
+ retvalue = rdcount;
+
+ for (; rdcount > 0; rdcount--)
+ buf[loop++] = ioread32(p + PCH_I2CDR);
+
+return_err:
+ /* disable buffer mode interrupts */
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+ /* restore the I2CMOD register */
+ iowrite32(i2cmod_prev, p + PCH_I2CMOD);
+
+ return retvalue;
+}
+
+/**
+ * pch_buffer_write() - Function to write data to I2C bus in buffer mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ */
+static s32 pch_buffer_write(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u32 loop;
+ u32 wrcount;
+ u32 msglen;
+ u32 i2cbufsub;
+ u32 addr;
+ u32 i2cbufslv_7_lsb;
+ u32 i2cbufslv_10_9_bit;
+ void __iomem *p = adap->pch_base_address;
+
+ /* initialize to invalid length, so that no sub address is tx-ed */
+ u32 subaddrlen = 5;
+ u32 i2cmod_prev;
+ s32 i;
+ u32 time_interval = i2c_adap->timeout;
+ u32 i2ctmr;
+ s32 retvalue;
+ u8 *buf;
+
+ msglen = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* get the current value of I2C mod register */
+ i2cmod_prev = ioread32(p + PCH_I2CMOD);
+ /* enable buffer mode */
+ iowrite32(PCH_BUFFER_MODE, p + PCH_I2CMOD);
+
+ time_interval = (time_interval <= 10) ? (time_interval) : (10);
+ /* value of I2CT = (Timeout interval * PCLK frequency)/ 8 */
+ i2ctmr = (time_interval * (pch_clk)) / 8;
+
+ iowrite32(i2ctmr, p + PCH_I2CTMR);
+
+ /* enable buffer mode interrupts */
+ iowrite32(BUFFER_MODE_INTR_ENBL, p + PCH_I2CBUFMSK);
+
+ /* if 10 bit addressing is selected */
+
+ if (msgs->flags & I2C_M_TEN) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s...ten bit addressing", __func__);
+ /* get the 8 LSBits */
+ i2cbufslv_7_lsb = (addr & I2C_ADDR_MSK);
+
+ /* get the 2 MSBits */
+ i2cbufslv_10_9_bit = ((addr & I2C_MSB_2B_MSK) << 1);
+
+ iowrite32(TEN_BIT_ADDR_DEFAULT | i2cbufslv_7_lsb |
+ i2cbufslv_10_9_bit, p + PCH_I2CBUFSLV);
+ } else {
+ iowrite32((addr & I2C_ADDR_MSK) << 1, p + PCH_I2CBUFSLV);
+ }
+
+ /* get sub address length, restrict to 4 bytes max */
+ subaddrlen =
+ (buf[0] <= SUB_ADDR_LEN_MAX) ? (buf[0]) : (SUB_ADDR_LEN_MAX);
+
+ for (i = (subaddrlen - 1), i2cbufsub = 0; i >= 0; i--) {
+ /* frame the sub address based on the length */
+ i2cbufsub |= (((u32) buf[2 - i]) << (8 * i));
+ }
+
+ /* subaddrlen bytes + the 1st field */
+ loop = subaddrlen + 1;
+
+ msglen -= loop;
+
+ /* write the sub address to the reg */
+ iowrite32(i2cbufsub, p + PCH_I2CBUFSUB);
+
+ /* clear buffers */
+ iowrite32(CLR_REG, p + PCH_I2CBUFLEV);
+
+ if (msglen >= BUF_LEN_MAX)
+ msglen = BUF_LEN_MAX;
+
+ for (wrcount = 0; wrcount < msglen; wrcount++) {
+ iowrite32(buf[loop++], p + PCH_I2CDR);
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "Buffer mode %x", (buf[loop] & 0xff));
+ }
+
+ /* set the number of bytes, transmission mode and sub address length */
+ iowrite32(((wrcount << 4) & PCH_BUF_TX) | subaddrlen,
+ p + PCH_I2CBUFFOR);
+ if ((pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT)) == -ETIME) {
+ retvalue = -ETIME;
+ goto return_err;
+ }
+
+ /* issue start bits */
+ pch_buff_mode_start(adap);
+
+ if (ioread32(p + PCH_I2CBUFSTA) & (I2CBMDZ_BIT | I2CBMAG_BIT)) {
+ retvalue = -EIO;
+ goto return_err;
+ }
+
+ if (pch_wait_for_xfer_complete(adap) == -ETIME) {
+ retvalue = -ETIME;
+ goto return_err;
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "pch_wait_for_xfer_complete return 0");
+ retvalue = wrcount;
+
+return_err:
+ /* disable buffer mode interrupts */
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+ /* restore the I2CMOD register */
+ iowrite32(i2cmod_prev, p + PCH_I2CMOD);
+
+ return retvalue;
+}
+
+/**
+ * pch_eeprom_sw_reset() - triggering EEPROM software reset
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ */
+static s32 pch_eeprom_sw_reset(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ void __iomem *p = adap->pch_base_address;
+ u32 time_interval = i2c_adap->timeout;
+ u32 i2ctmr;
+ u32 i2cmod_prev;
+ u32 pch_pattern;
+ s32 ret_val;
+
+ /* get the current value of I2C mod register */
+ i2cmod_prev = ioread32(p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ pch_setbit((adap->pch_base_address), PCH_I2CMOD,
+ EEPROM_SW_RST_MODE);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CMOD %x\n",
+ __func__, ioread32(p + PCH_I2CMOD));
+ iowrite32(EEPROM_RST_INTR_ENBL, p + PCH_I2CESRMSK);
+
+ if (time_interval > 10)
+ time_interval = 10;
+
+ /* value of I2CT = (Timeout interval * PCLK frequency)/ 8 */
+ i2ctmr = (time_interval * (pch_clk)) / 8;
+
+ iowrite32(i2ctmr, p + PCH_I2CTMR);
+
+ /* get the EEPROM reset pattern */
+ pch_pattern = (u32) (*(msgs->buf));
+
+ /* mode 1 & 2 are used for buffer mode selection */
+ pch_pattern -= 2;
+
+ iowrite32(pch_pattern, p + PCH_I2CESRFOR);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CESRFOR %x\n",
+ __func__, ioread32(p + PCH_I2CESRFOR));
+
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == 0) {
+ pch_eeprom_swrst_start(adap);
+ ret_val = pch_wait_for_xfer_complete(adap);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "pch_wait_for_xfer_complete return =%d\n", ret_val);
+ iowrite32(i2cmod_prev, p + PCH_I2CMOD);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return=%d\n", __func__, ret_val);
+
+ return ret_val;
+}
+
+/**
+ * pch_cb() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_cb(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ u32 i2c_mode;
+ u32 i2c_interrupt;
+ void __iomem *p = adap->pch_base_address;
+
+ reg_val = ioread32(p + PCH_I2CMOD);
+ /* get the current mode of operation */
+ i2c_mode = reg_val & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ i2c_interrupt = false;
+ switch (i2c_mode) {
+ case NORMAL_MODE:
+ reg_val = ioread32(p + PCH_I2CSR);
+ reg_val &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+
+ if (reg_val != 0) {
+ if (I2CMAL_BIT & reg_val)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & reg_val)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address),
+ PCH_I2CSR, reg_val);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : PCH_I2CSR = %x\n",
+ __func__, ioread32(p + PCH_I2CSR));
+
+ i2c_interrupt = true;
+ }
+ break;
+
+ case BUFFER_MODE:
+ reg_val = ioread32(p + PCH_I2CBUFSTA);
+ reg_val &= BUFFER_MODE_MASK;
+ if (reg_val != 0) {
+ /* there is a co-relation between the buffer
+ * mode interrupt flags' bit */
+ /* positions and the flag positions in event
+ * flag. for e.g. I2CBMFI is at position */
+ /* 0 in the I2CBUFSTA register. its position
+ * in the event flag is 2, hence left shifting
+ */
+ adap->pch_event_flag |= ((reg_val) << 2);
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address),
+ PCH_I2CBUFSTA, reg_val);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : PCH_I2CBUFSTA = %x\n", __func__,
+ ioread32(p + PCH_I2CBUFSTA));
+
+ i2c_interrupt = true;
+ }
+ break;
+
+ case EEPROM_SR_MODE:
+ reg_val = ioread32(p + PCH_I2CESRSTA);
+ reg_val &= (I2CESRFI_BIT | I2CESRTO_BIT);
+ if (reg_val != 0) {
+ adap->pch_event_flag |= ((reg_val) << 7);
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address),
+ PCH_I2CESRSTA, reg_val);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : PCH_I2CESRSTA = %x\n", __func__,
+ ioread32(p + PCH_I2CESRSTA));
+
+ i2c_interrupt = true;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ if (i2c_interrupt)
+ wake_up_interruptible(&pch_event);
+
+ return (i2c_interrupt) ? (PCH_EVENT_SET) : (PCH_EVENT_NONE);
+}
+
+
+/**
+ * pch_xfer() - transfer data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret) {
+ ret = -ERESTARTSYS;
+ goto return_err_nomutex;
+ }
+ if (adap->p_adapter_info->pch_suspended == false) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s adap->p_adapter_info->pch_suspended is %d\n",
+ __func__, adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "adap->pch_xfer_in_progress is %d\n",
+ adap->pch_xfer_in_progress);
+ pmsg = &msgs[0];
+ status = pmsg->flags;
+ /* special commands for PCH I2C driver */
+ if (status &
+ (PCH_EEPROM_SW_RST_MODE_ENABLE | PCH_BUFFER_MODE_ENABLE)) {
+ if (status & PCH_EEPROM_SW_RST_MODE_ENABLE) {
+ /* check whether EEPROM sw reset is enabled */
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_eeprom_sw_reset."
+ "Invoking I2C_MODE_SEL :flag= 0x%x\n",
+ __func__, status);
+ ret = pch_eeprom_sw_reset(i2c_adap, pmsg);
+ } else {
+ adap->pch_buff_mode_en =
+ (pmsg->buf[0] == 1) ?
+ (PCH_BUFFER_MODE_ENABLE) : (pmsg->buf[0]);
+ ret = 0;
+ }
+ /* transfer completed */
+ adap->pch_xfer_in_progress = false;
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "adap->pch_xfer_in_progress is %d. "
+ "After mode selection %s return = %d\n",
+ adap->pch_xfer_in_progress, __func__, ret);
+ goto return_ok;
+ }
+
+ ret = -EBUSY;
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n",
+ status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+
+ if ((status & PCH_BUFFER_MODE_ENABLE)
+ && (msglen != 0)) {
+ /* Buffer mode cannot be used for transferring
+ * 0 byte data. Hence when buffer mode is
+ * enabled and 0 byte transfer is requested,
+ * normal mode transfer will be used */
+ if (status & (I2C_M_RD)) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_buffer_read\n",
+ __func__);
+ ret = pch_buffer_read(i2c_adap, pmsg);
+ } else {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_buffer_write\n",
+ __func__);
+ ret = pch_buffer_write(i2c_adap, pmsg);
+ }
+ } else {
+ if (status & (I2C_M_RD)) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_readbytes\n",
+ __func__);
+ ret = pch_readbytes(i2c_adap, pmsg,
+ (i + 1 == num),
+ (i == 0));
+ } else {
+ dev_info(adap->pch_adapter.dev.parent,
+ "%s invoking pch_writebytes\n",
+ __func__);
+ ret = pch_writebytes(i2c_adap, pmsg,
+ (i + 1 == num),
+ (i == 0));
+ }
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "adap->pch_xfer_in_progress is %d\n",
+ adap->pch_xfer_in_progress);
+ } else {
+ ret = -EBUSY;
+ }
+return_ok:
+ mutex_unlock(&pch_mutex);
+return_err_nomutex:
+ dev_dbg(adap->pch_adapter.dev.parent, "%s return:%d\n\n\n\n",
+ __func__, ret);
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : PCH_I2CESRMSK = %x\n",
+ __func__, ioread32(p + PCH_I2CESRMSK));
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : PCH_I2CBUFMSK = %x\n",
+ __func__, ioread32(p + PCH_I2CBUFMSK));
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
+
+ if (adap_info == NULL) {
+ dev_err(&pdev->dev, "Memory allocation failed FAILED");
+ ret = -ENOMEM;
+ goto return_err;
+ }
+
+ dev_dbg(&pdev->dev,
+ "%s kzalloc invoked successfully and adap_info valu = %p\n",
+ __func__, adap_info);
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
+ goto err_pci_enable;
+ }
+
+ dev_dbg(&pdev->dev, "%s pci_enable_device returns %d\n", __func__, ret);
+
+ ret = pci_request_regions(pdev, MODULE_NAME);
+ if (ret) {
+ dev_err(&pdev->dev, "pci_request_regions FAILED");
+ goto err_pci_req;
+ }
+
+ dev_dbg(&pdev->dev, "%s pci_request_regions returns %d\n",
+ __func__, ret);
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ dev_err(&pdev->dev, "pci_iomap FAILED");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ dev_dbg(&pdev->dev, "%s pci_iomap invoked successfully\n", __func__);
+ adap_info->pch_suspended = false;
+
+ pch_entcb(pch_cb);
+ dev_dbg(&pdev->dev, "%s pch_entcb invoked successfully\n", __func__);
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, "pch_i2c");
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ dev_err(&pdev->dev, "i2c_add_adapter FAILED");
+ goto err_i2c_add_adapter;
+ }
+
+ dev_dbg(&pdev->dev,
+ "i2c_add_adapter returns %d for channel-%d\n", ret, i);
+ pch_init(&adap_info->pch_data[i]);
+ dev_dbg(&pdev->dev, "pch_init invoked successfully\n");
+ }
+
+ ret = request_irq(pdev->irq, &pch_handler, IRQF_SHARED,
+ MODULE_NAME, adap_info);
+
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq Failed\n");
+ goto err_request_irq;
+ }
+
+ dev_dbg(&pdev->dev, "request_irq returns %d pch_probe returns.\n", ret);
+ pci_set_drvdata(pdev, adap_info);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+return_err:
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+ dev_dbg(&pdev->dev, "invoked function pci_get_drvdata successfully\n");
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+
+ if (i == (PCH_MAX_CHN - 1)) {
+ free_irq(pdev->irq, adap_info);
+ dev_dbg(&pdev->dev, "free_irq invoked successfully\n");
+ }
+
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ dev_dbg(&pdev->dev, "invoked i2c_del_adapter successfully\n");
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ dev_dbg(&pdev->dev, "pci_iounmap invoked successfully\n");
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+ dev_dbg(&pdev->dev, "pci_release_regions invoked successfully\n");
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+ dev_dbg(&pdev->dev,
+ "pci_disable_device invoked success.%s invoked success\n",
+ __func__);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ dev_dbg(&pdev->dev, "invoked function pci_get_drvdata successfully\n");
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* It is assumed that any pending transfer will
+ * be completed after the delay
+ */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ dev_dbg(&pdev->dev,
+ "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08),
+ ioread32(p + 0x30),
+ ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ dev_err(&pdev->dev, "pci_save_state failed\n");
+ return ret;
+ }
+
+ dev_dbg(&pdev->dev, "Invoked pci_save_state successfully\n");
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ dev_dbg(&pdev->dev, "Invoked pci_enable_wake successfully\n");
+
+ pci_disable_device(pdev);
+ dev_dbg(&pdev->dev, "Invoked pci_disable_device successfully\n");
+
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+ dev_dbg(&pdev->dev,
+ "Invoked pci_set_power_state successfully. %s returns 0\n",
+ __func__);
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ dev_dbg(&pdev->dev, "invoked function pci_get_drvdata successfully\n");
+
+ pci_set_power_state(pdev, PCI_D0);
+ dev_dbg(&pdev->dev, "Invoked pci_set_power_state successfully\n");
+
+ pci_restore_state(pdev);
+ dev_dbg(&pdev->dev, "Invoked pci_restore_state successfully\n");
+
+ if (pci_enable_device(pdev) < 0) {
+ dev_err(&pdev->dev, "pci_enable_device failed in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ dev_dbg(&pdev->dev, "Invoked pci_enable_wake successfully\n");
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ dev_dbg(&pdev->dev, "Invoked pch_init successfully\n");
+
+ adap_info->pch_suspended = false;
+
+ dev_dbg(&pdev->dev, "%s return 0\n", __func__);
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = "pch_i2c",
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
diff --git a/drivers/i2c/busses/i2c-pch.h b/drivers/i2c/busses/i2c-pch.h
new file mode 100644
index 0000000..f140ce0
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __PCH_HAL_H__
+#define __PCH_HAL_H__
+
+#define PCH_MAX_CHN 1 /* Maximum I2C channels available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define I2C_MODE_SEL 0x711 /* for mode selection */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+
+#define MODULE_NAME "pch_i2c"
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+#endif
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index e0694e4..0df77a7 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -36,6 +36,7 @@
#include <linux/i2c-dev.h>
#include <linux/jiffies.h>
#include <linux/uaccess.h>
+#include "busses/i2c-pch.h"
static struct i2c_driver i2cdev_driver;
@@ -147,6 +148,11 @@ static ssize_t i2cdev_read(struct file *file, char __user *buf, size_t count,
if (tmp == NULL)
return -ENOMEM;
+ if (copy_from_user(tmp, buf, count)) {
+ kfree(tmp);
+ return -EFAULT;
+ }
+
pr_debug("i2c-dev: i2c-%d reading %zu bytes.\n",
iminor(file->f_path.dentry->d_inode), count);
@@ -372,6 +378,12 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
struct i2c_client *client = file->private_data;
unsigned long funcs;
+ unsigned long pch_mode;
+ int ret;
+
+ struct i2c_msg msg;
+ unsigned char msgbuf[1];
+
dev_dbg(&client->adapter->dev, "ioctl, cmd=0x%02x, arg=0x%02lx\n",
cmd, arg);
@@ -427,6 +439,22 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
*/
client->adapter->timeout = msecs_to_jiffies(arg * 10);
break;
+ case I2C_MODE_SEL:
+ pch_mode = arg;
+
+ if (pch_mode <= 4) {
+ msgbuf[0] = pch_mode;
+ msg.buf = msgbuf;
+ msg.len = 1;
+ msg.flags = (pch_mode <= 1) ? \
+ (PCH_BUFFER_MODE_ENABLE) : \
+ (PCH_EEPROM_SW_RST_MODE_ENABLE);
+ ret = i2c_transfer(client->adapter, &msg, 1);
+ } else {
+ printk(KERN_ERR "I2C mode sel:Invalid mode\n");
+ ret = -EINVAL;
+ }
+ return ret;
default:
/* NOTE: returning a fault code here could cause trouble
* in buggy userspace code. Some old kernel bugs returned
--
1.6.0.6
--
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