Hi , Looks like there is some discrepancy with the mxc i2c driver. In this portion of the mxc_i2c_stop() routine, the MSTA bit is cleared(1to 0) to generate a stop condition but there is no state check whatsoever before for the IBB bit (bus busy bit is set or not) while (retry-- && ((sr & MXC_I2SR_IBB))) { udelay(3); sr = readw(dev->membase + MXC_I2SR); I am not sure what SCL frequency has been tested with for the "udelay(3)". Is that a sufficient wait on busses set to run on the traditional slow rate(bit rate upto 100 kbps? I am curious. Thanks, Alfred. -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html