On Wed, May 29, 2024 at 01:33:35PM +0100, Andrew Cooper wrote: > Seems I've gained a reputation... Yes you have. You have this weird interest in very deep uarch details that I can't share. Not at that detail. :-P > jmp 1f dates back to ye olde 8086, which started the whole trend of the > instruction pointer just being a figment of the ISA's imagination[1]. > > Hardware maintains the pointer to the next byte to fetch (the prefetch > queue was up to 6 bytes), and there was a micro-op to subtract the > current length of the prefetch queue from the accumulator. > > In those days, the prefetch queue was not coherent with main memory, and > jumps (being a discontinuity in the instruction stream) simply flushed > the prefetch queue. > > This was necessary after modifying executable code, because otherwise > you could end up executing stale bytes from the prefetch queue and then > non-stale bytes thereafter. (Otherwise known as the way to distinguish > the 8086 from the 8088 because the latter only had a 4 byte prefetch queue.) Thanks - that certainly wakes up a long-asleep neuron in the back of my mind... > Anyway. It's how you used to spell "serialising operation" before that > term ever entered the architecture. Linux still supports CPUs prior to > the Pentium, so still needs to care about prefetch queues in the 486. > > However, this example appears to be in 64bit code and following a write > to CR4 which will be fully serialising, so it's probably copy&paste from > 32bit code where it would be necessary in principle. Yap, fully agreed. We could try to remove it and see what complains. Nikolay, wanna do a patch which properly explains the situation? > https://www.righto.com/2023/01/inside-8086-processors-instruction.html#fn:pc > > In fact, anyone who hasn't should read the entire series on the 8086, > https://www.righto.com/p/index.html Oh yeah, already bookmarked. Thanks Andy! -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
