Hi Bjorn, Alexander, Thanks for attending and raising question during our talk on "Instant Detection of Virtual Devices". Recoding link for reference: https://youtu.be/0mIO54oQ2zI?t=7151 Bjorn, I hope I understood your questions properly and replied. If some doubts please let us know. Alexander, you wanted to know about following (please correct if we understood something wrong): Why we still have ~300 read/write, even after having following progressive approaches: - MMIO Direct Read - Skip write to PCIe configs - Pre-config of PCIe configs [1] remaining writes: As per PCI specification, needs to perform following operation to read BAR addr and size: - Read current value from BAR - Write all-ones to BAR - Read new value from BAR - Write original value back to BAR Same applies to following configs as well: - BARs - I/O Base/Limit - Memory Base/Limit - Prefetchable Memory Base/Limit - Prefetchable Base Limit/Upper 32 bits - I/O Base/Limit Upper 16 bits These write operations couldn't be eliminated with our progressive approaches and major of remaining writes are because of these operations. [2] remaining reads: Before initialize MMIO, guest performs very few PCI config reads over PIO. I guess these can't be eliminated. --Ajay
