On Thu, Apr 15, 2021 at 01:43:37PM +0000, Vineeth Pillai wrote: > Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies > support for enlightened TLB flush. With this enlightenment enabled, > ASID invalidations flushes only gva->hpa entries. To flush TLB entries > derived from NPT, hypercalls should be used > (HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList) > > Signed-off-by: Vineeth Pillai <viremana@xxxxxxxxxxxxxxxxxxx> > --- > arch/x86/include/asm/hyperv-tlfs.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h > index 606f5cc579b2..005bf14d0449 100644 > --- a/arch/x86/include/asm/hyperv-tlfs.h > +++ b/arch/x86/include/asm/hyperv-tlfs.h > @@ -133,6 +133,15 @@ > #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) > #define HV_X64_NESTED_MSR_BITMAP BIT(19) > > +/* > + * This is specific to AMD and specifies that enlightened TLB flush is > + * supported. If guest opts in to this feature, ASID invalidations only > + * flushes gva -> hpa mapping entries. To flush the TLB entries derived > + * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace > + * or HvFlushGuestPhysicalAddressList). > + */ > +#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) > + This is not yet documented in TLFS, right? I can't find this bit in the latest edition (6.0b). My first thought is the comment says this is AMD specific but the name is rather generic. That looks a bit odd to begin with. Wei. > /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ > #define HV_PARAVISOR_PRESENT BIT(0) > > -- > 2.25.1 >
