On Thu, Oct 26, 2023 at 11:43:46PM -0500, Lakshmi Yadlapati wrote: > The MAX31785 has shown erratic behaviour across multiple system > designs, unexpectedly clock stretching and NAKing transactions. > > Experimentation shows that this seems to be triggered by a register access > directly back to back with a previous register write. Experimentation also > shows that inserting a small delay after register writes makes the issue go > away. > > Use a similar solution to what the max15301 driver does to solve the same > problem. Create a custom set of bus read and write functions that make sure > that the delay is added. > > Signed-off-by: Lakshmi Yadlapati <lakshmiy@xxxxxxxxxx> [ ... ] > + if (delta < MAX31785_WAIT_DELAY_US) > + usleep_range(MAX31785_WAIT_DELAY_US - delta, > + MAX31785_WAIT_DELAY_US); This means the driver will now wait up to 250 uS even if it only has to wait for 1 uS. But I really don't want to wait or argue further, so I just applied the patch as-is. Guenter
