On Mon, 2021-11-29 at 14:43 +0800, Billy Tsai wrote:
[...]
> + ret = clk_prepare_enable(priv->clk);
> + if (ret)
> + return dev_err_probe(dev, ret, "Couldn't enable clock\n");
> +
> + ret = reset_control_deassert(priv->reset);
> + if (ret) {
> + dev_err_probe(dev, ret, "Couldn't deassert reset control\n");
> + goto err_disable_clk;
> + }
Is there any reason to keep the clocks running and the controller out of
reset while the PWM outputs are disabled?
regards
Philipp
