Re: [PATCH] pinctrl: cy8c95x0: Cache muxed registers

[Andy Shevchenko <andy.shevchenko@xxxxxxxxx>]

On Tue, May 14, 2024 at 12:02 PM Mark Brown <broonie@xxxxxxxxxx> wrote:
> On Tue, May 14, 2024 at 11:55:06AM +0300, Andy Shevchenko wrote:
>
> > It's about introducing pages of virtual registers (from regmap p.o.v.)
> > to access the banks of selectable registers. The cache most likely
> > will be the same, i.e. MAPPLE_TREE.
>
> If there's paging of registers then regmap supports this with the ranges
> feature, you can tell regmap where the window is in the physical
> register map and which register to use to switch pages and have regmap
> export the underlying registers as a linear range of virtual registers.

In this chip there are two ranges that are dependent on a selector,
one is for port selection (which the original change is about) and
another is for PWM (IIRC). Note that they are orthogonal to each
other, meaning they have their own selector registers.

-- 
With Best Regards,
Andy Shevchenko