On 10/13/23 16:59, Krzysztof Kozlowski wrote:
Existing Qualcomm SoCs have the LPASS pin controller slew rate control in separate register, however this will change with upcoming Qualcomm SoCs. The slew rate will be part of the main register for pin configuration, thus second device IO address space is not needed. Prepare for supporting new SoCs by adding flag customizing the driver behavior for slew rate. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> --- Changes in v2: 1. Reversed xmas tree v1: https://lore.kernel.org/all/20230901090224.27770-1-krzysztof.kozlowski@xxxxxxxxxx/ ---
Only because I know it'll be used soon: Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Konrad
