Re: [PATCH v8 char-misc-next 2/5] misc: microchip: pci1xxxx: Add OTP Functionality to read and write into OTP bin sysfs

[<VaibhaavRam.TL@xxxxxxxxxxxxx>]

On Wed, 2023-03-29 at 12:01 +0200, Greg KH wrote:
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> On Tue, Mar 28, 2023 at 08:10:05PM +0530, Vaibhaav Ram T.L wrote:
> > From: Kumaravel Thiagarajan <kumaravel.thiagarajan@xxxxxxxxxxxxx>
> > 
> > Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
> > industrial, and automotive applications. This switch integrates OTP
> > and EEPROM to enable customization of the part in the field.
> > This patch adds the OTP functionality to support the same.
> 
> Why not just use the in-kernel eeprom api instead of creating your
> own
> custom user/kernel api?  Why is this so special to deserve that?
Unlike other in-Kernel EEPROM APIs, this OTP is not accessible through
any of the i2c/spi buses available to the kernel.

It is only accessible through the register interface available in the
OTP controller of the PCI1XXXX device.

The architecture of the device was discussed @
https://lore.kernel.org/all/Y+9HOdHGqmPP%2FUde@xxxxxxxxx/
> > +struct pci1xxxx_otp_eeprom_device {
> > +     struct auxiliary_device *pdev;
> > +     void __iomem *reg_base;
> > +     bool is_eeprom_present;
> 
> This field is never used, why have it?
This should have appeared in EEPROM patch. Will change it.
> 
> > +};
> 
> Why does this need to be in the .h file and not in the .c file?
This structure is shared by both mchp_pci1xxxx_gp.c and
mchp_pci1xxxx_otpe2p.c files.
> 
> thanks,
> 
> greg k-h