Re: [PATCH v5 2/2] pinctrl: pinctrl-mlxbf: Add pinctrl driver support

[Andy Shevchenko <andy.shevchenko@xxxxxxxxx>]

On Wed, Mar 15, 2023 at 12:16 AM Asmaa Mnebhi <asmaa@xxxxxxxxxx> wrote:
>
> NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs
> or take the default hardware functionality. Add a driver for
> the pin muxing.

...

>  drivers/pinctrl/pinctrl-mlxbf3.c | 318 +++++++++++++++++++++++++++++++

Ah, cool, so it's a typo in the GPIO driver then.

...

> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>

+ err.h
+ types.h

...

> +struct mlxbf3_pinctrl {
> +       void __iomem *fw_ctrl_set0;
> +       void __iomem *fw_ctrl_clr0;
> +       void __iomem *fw_ctrl_set1;
> +       void __iomem *fw_ctrl_clr1;

> +       struct device *dev;
> +       struct pinctrl_dev *pctl;

Depending on what is used more often in the code you can shuffle the
order and save a few bytes in the generated code. You may play with
bloat-o-meter to check.

> +       struct pinctrl_gpio_range gpio_range;
> +};

...

> +static const char * const mlxbf3_pinctrl_single_group_names[] = {
> +       "gpio0", "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",  "gpio6", "gpio7",
> +       "gpio8",  "gpio9",  "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
> +       "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> +       "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
> +       "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
> +       "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
> +       "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55"

You can leave the trailing comma.

> +};

-- 
With Best Regards,
Andy Shevchenko