Re: [PATCH v2 9/9] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

Hi Prabhakar,

On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
> ETH1 respectively.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> @@ -6,6 +6,7 @@
>   */
>
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
>  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>
>  / {
> @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
>                 compatible = "ethernet-phy-id0022.1640",
>                              "ethernet-phy-ieee802.3-c22";
>                 reg = <7>;
> +               interrupt-parent = <&irqc>;

Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have
the irqc node yet, so I cannot take this as-is.

> +               interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
>                 rxc-skew-psec = <2400>;
>                 txc-skew-psec = <2400>;
>                 rxdv-skew-psec = <0>;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds