On Thu, Nov 17, 2022 at 01:07:59PM +0200, Andy Shevchenko wrote: > > This is a continuation of the previously applied PWM LPSS cleanup series. > Now, we would like to enable PWM optional feature that may be embedded > into Intel pin control IPs (starting from Sky Lake platforms). > > I would like to route this via Intel pin control tree with issuing > an immutable branch for both PINCTRL and PWM subsystems, but I'm > open for other suggestions. > > Hans, I dared to leave your Rb tags, however the patches are slightly > differ, because of the Uwe's suggestion on how to handle the missing > headers. I hope you are okay with that. If not, please comment what > must be amended then. > > Uwe, the patches 3 and 6 still need your blessing. Uwe, do you think they are ready to go? -- With Best Regards, Andy Shevchenko