RE: [PATCH v3 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding

[Biju Das <biju.das.jz@xxxxxxxxxxxxxx>]

Hi Rob,

Thanks for the feedback.

> Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
> binding
> 
> On Fri, Nov 04, 2022 at 03:19:34PM +0000, Biju Das wrote:
> > Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v2->v3:
> >  * Removed Rb tag from Rob as there are some changes introduced.
> >  * Added companion property, so that poeg can link with gpt device
> >  * Documented renesas,id, as identifier for POEGG{A,B,C,D}.
> >  * Updated the example.
> > v1->v2:
> >  * Updated the description.
> > REF->v1:
> >  * Modelled as pincontrol as most of its configuration is intended to be
> >    static.
> >  * Updated reg size in example.
> > ---
> >  .../bindings/pinctrl/renesas,rzg2l-poeg.yaml  | 86
> > +++++++++++++++++++
> >  1 file changed, 86 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> > b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> > new file mode 100644
> > index 000000000000..8adf01682de5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
> > +++ l
> > @@ -0,0 +1,86 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +
> > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > +
> > +description: |
> > +  The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT)
> > +can be
> > +  disabled by using the port output enabling function for the GPT (POEG).
> > +  Specifically, either of the following ways can be used.
> > +  * Input level detection of the GTETRGA to GTETRGD pins.
> > +  * Output-disable request from the GPT.
> > +  * SSF bit setting(ie, by setting POEGGn.SSF to 1)
> > +
> > +  The state of the GTIOCxA and the GTIOCxB pins when the output is
> > + disabled,  are controlled by the GPT module.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}
> > +          - renesas,r9a07g054-poeg  # RZ/V2L
> > +      - const: renesas,rzg2l-poeg
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    maxItems: 1
> > +
> > +  companion:
> 
> Also, needs a vendor prefix. The companion is the GPT, right? Perhaps
> 'renesas,gpt' instead.


Yes, it is GPT. Will use 'renesas,gpt'.

Cheers,
Biju


> 
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: phandle of a companion.