Hi Andy, On Tue, Nov 01, 2022 at 05:56:36PM +0200, Andy Shevchenko wrote: > This is a continuation of the previously applied PWM LPSS clean up. > Now, we would like to enable PWM optional feature that may be embedded > into Intel pin control IPs (starting from Sky Lake platforms). > > I would like to route this via Intel pin control tree with issuing > an immutable branch for both PINCTRL and PWM subsystems, but I'm > open for other suggestions. > > Hans, I dared to leave your Rb tags, however the patches are slighly > differ, because of the Uwe's suggestion on how to handle the missing > headers. I hope you is okay with that. If not, please comment what > must be ammended then. > > Cc: Hans de Goede <hdegoede@xxxxxxxxxx> > Cc: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> > > Andy Shevchenko (6): > pwm: Add a stub for devm_pwmchip_add() > pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS > pwm: lpss: Include headers we are direct user of > pwm: lpss: Allow other drivers to enable PWM LPSS > pwm: lpss: Add pwm_lpss_probe() stub > pinctrl: intel: Enumerate PWM device when community has a capabilitty Looks good to me. For the entire series, Reviewed-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>