From: Emil Renner Berthing <kernel@xxxxxxxx> This cache controller is also used on the StarFive JH7100 and JH7110 SoCs. Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxxxxxxxx> --- Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index ca3b9be58058..ba29ecfd3a92 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -24,6 +24,8 @@ select: enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache + - starfive,jh7110-ccache required: - compatible @@ -35,6 +37,8 @@ properties: - enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache + - starfive,jh7110-ccache - const: cache - items: - const: microchip,mpfs-ccache -- 2.17.1