On Fri, Sep 2, 2022 at 8:15 AM Qingtao Cao <qingtao.cao.au@xxxxxxxxx> wrote: > > When EXAR xr17v35x chips are cascaded in order to access the MPIO registers > (part of the Device Configuration Registers) of the secondary chips, an offset > needs to be applied based on the number of primary chip's UART channels. > > Signed-off-by: Qingtao Cao <qingtao.cao@xxxxxxxx> > --- Applied, thanks! Bart
Re: [v3 PATCH 1/1] gpio: exar: access MPIO registers on cascaded chips
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- Subject: Re: [v3 PATCH 1/1] gpio: exar: access MPIO registers on cascaded chips
- From: Bartosz Golaszewski <brgl@xxxxxxxx>
- Date: Sun, 4 Sep 2022 22:25:43 +0200
- In-reply-to: <20220902061434.46995-1-qingtao.cao@digi.com>
- References: <20220902061434.46995-1-qingtao.cao@digi.com>
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- [v3 PATCH 1/1] gpio: exar: access MPIO registers on cascaded chips
- From: Qingtao Cao
- [v3 PATCH 1/1] gpio: exar: access MPIO registers on cascaded chips
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