On Tue, Aug 23, 2022 at 4:50 AM Chen Jeffy <jeffy.chen@xxxxxxxxxxxxxx> wrote: > The thing is, we are currently toggling the trigger mode to make sure it > matches the current GPIO level (e.g. level low -> rising edge mode), > than ack it in gpio IRQ handler. Yes this is an old trick, I don't know if I invented it again for Linux in commit cc890cd78acd7ab03442907d354b6af34e973cb3 in 2011, surely the trick must be well known. Back then I did it like this: + val = readl(U300_PIN_REG(offset, icr)); + /* Set mode depending on state */ + if (u300_gpio_get(&gpio->chip, offset)) { + /* High now, let's trigger on falling edge next then */ + writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); + dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", + offset); + } else { + /* Low now, let's trigger on rising edge next then */ + writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); + dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", + offset); + } Notice that I read the current level of the raw input to decide what the next trigger should be. The Rockchip driver does not do this, maybe that works better? Yours, Linus Walleij