Always configure GPIO pins which are used as interrupt source as INPUTs. In case the default pin configuration is OUTPUT, or the prior stage does configure the pins as OUTPUT, then Linux will not reconfigure the pin as INPUT and no interrupts are received. Always configure interrupt source GPIO pin as input to fix the above case. Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") Signed-off-by: Marek Vasut <marex@xxxxxxx> Cc: Bartosz Golaszewski <bgolaszewski@xxxxxxxxxxxx> Cc: Linus Walleij <linus.walleij@xxxxxxxxxx> Cc: Loic Poulain <loic.poulain@xxxxxxxxxx> Cc: Marc Zyngier <maz@xxxxxxxxxx> Cc: NXP Linux Team <linux-imx@xxxxxxx> Cc: Peng Fan <peng.fan@xxxxxxx> Cc: Shawn Guo <shawnguo@xxxxxxxxxx> --- V2: Actually update and clear bits in GDIR register V3: Rebase on top of new patch 1/2, expand CC list, add Fixes tag V4: No change --- drivers/gpio/gpio-mxc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 75e7aceecac0a..f4cadbf30c6b8 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -149,7 +149,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; unsigned long flags; - u32 bit, val; + u32 bit, val, dir; u32 gpio_idx = d->hwirq; int edge; void __iomem *reg = port->base; @@ -208,6 +208,10 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(1 << gpio_idx, port->base + GPIO_ISR); + dir = readl(port->base + GPIO_GDIR); + dir &= ~BIT(gpio_idx); + writel(dir, port->base + GPIO_GDIR); + spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); return 0; -- 2.35.1