D1 contains a pin controller similar to previous SoCs, but with some register layout changes. It includes 6 interrupt-capable pin banks. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Tested-by: Heiko Stuebner <heiko@xxxxxxxxx> Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> --- Changes in v2: - Drop D1s compatible for now, due to ongoing discussion .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 6bfa46073791..d19d65c870aa 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -46,6 +46,7 @@ properties: - allwinner,sun8i-v3s-pinctrl - allwinner,sun9i-a80-pinctrl - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun20i-d1-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl - allwinner,sun50i-a100-pinctrl @@ -178,6 +179,18 @@ allOf: minItems: 7 maxItems: 7 + - if: + properties: + compatible: + enum: + - allwinner,sun20i-d1-pinctrl + + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + - if: properties: compatible: -- 2.35.1