Re: [PATCH v2 2/2] pinctrl: renesas: Add RZ/V2M pin and gpio controller driver

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

Hi Phil,

On Fri, Jun 24, 2022 at 10:49 AM Phil Edworthy
<phil.edworthy@xxxxxxxxxxx> wrote:
> Add support for pin and gpio controller driver for RZ/V2M SoC.
> Based on the RZ/G2L driver.
>
> Note that the DETDO and DETMS dedicated pins are currently not
> documented in the HW manual as to which pin group they are in.
> HW team have since said that the output level of V1.8V I/O group 4
> (for MD0-7, and debugger) is the same as the 1.8V IO group 3.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v2:
>  - Lots of small fixes based on Geert's review
>  - Remove PIN_CONFIG_INPUT_ENABLE as it is not appropriate

Thanks for the update!

> --- /dev/null
> +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c

> +#define DRV(n)                 ((n) < RZV2M_DEDICATED_PORT_IDX ? \
> +                               (0x28 + (n) * 0x40) : 0x590)
> +#define SR(n)                  ((n) < RZV2M_DEDICATED_PORT_IDX ? \
> +                               (0x2c + (n) * 0x40) : 0x594)

If you don't mind, I'll reformat this slightly while applying:

    #define DRV(n)          ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 +
(n) * 0x40) \
                                                            : 0x590)
    #define SR(n)           ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c +
(n) * 0x40) \
                                                            : 0x594)

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-pinctrl-for-v5.20.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds