Hi! Jernej, sorry to have kept you waiting. On Wed, May 26, 2022 at 11:52 PM Jernej Škrabec <jernej.skrabec@xxxxxxxxx> wrote: > You didn't explain how issue manifests. How did you find it? I noticed this problem when tried to pull-down a pin at kernel 5.3.11. sunxi_pconf_set uses sunxi_pconf_reg to get offset and shift. sunxi_pconf_reg uses the next functions to calculate register offset: sunxi_dlevel_reg sunxi_dlevel_offset sunxi_pull_reg sunxi_pull_offset These functions calculate the offset relative to the pinctrl address. Let's consider the sunxi_pconf_reg's output with the following arguments: pin = 354 (PL2) param = PIN_CONFIG_BIAS_PULL_UP So the sunxi_pull_reg is called and it returns "0x1a8". This value too high to be register offset :) But with my patch: pin_base = 352 pin = 354 - 352 = 2 (PL2) param = PIN_CONFIG_BIAS_PULL_UP And sunxi_pull_reg returns "0x1c" as expected. According to the datasheet [1] (page 349) it's the PL_PULL register. P.S. sunxi_pconf_get calculates the pin number in the same way (line 490). --- [1] https://linux-sunxi.org/images/4/4b/Allwinner_H3_Datasheet_V1.2.pdf Best regards, Andrei Lalaev