Hi,
Thanks for having a look.
On Fri, Apr 22, 2022 at 07:16:13PM +0100, Robin Murphy wrote:
> On 2022-04-22 18:09, Sebastian Reichel wrote:
> > ...
> > + cpu_l0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x0>;
> > + enable-method = "psci";
> > + capacity-dmips-mhz = <530>;
> > + clocks = <&scmi_clk SCMI_CLK_CPUL>;
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_cache_l0>;
> > + #cooling-cells = <2>;
> > + dynamic-power-coefficient = <228>;
> > + };
>
> Is there any particular reason for not including more of the CPUs?
Yes, see below.
> > + its: interrupt-controller@fe640000 {
> > + compatible = "arm,gic-v3-its";
> > + msi-controller;
> > + #msi-cells = <1>;
> > + reg = <0x0 0xfe640000 0x0 0x20000>;
> > + };
> > + };
>
> Does the ITS (and other bits related to GIC memory accesses) actually work,
> or will we have more of the same issues as RK356x?
The GIC in RK3588 is has the same shareability limitation as the RK356x,
but fixed the 32bit limitation. That's why I just added the boot cpu core
for now; adding any other cpu core breaks the boot without the downstream
shareability patch and I'm still investigating.
-- Sebastian
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