Re: [PATCH v1 3/6] gpio: realtek-otto: Support per-cpu interrupts

[Marc Zyngier <maz@xxxxxxxxxx>]

On Thu, 21 Apr 2022 00:04:16 +0100,
Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:
> 
> On Sat, Apr 9, 2022 at 9:56 PM Sander Vanheule <sander@xxxxxxxxxxxxx> wrote:
> 
> > On SoCs with multiple cores, it is possible that the GPIO interrupt
> > controller supports assigning specific pins to one or more cores.
> >
> > IRQ balancing can be performed on a line-by-line basis if the parent
> > interrupt is routed to all available cores, which is the default upon
> > initialisation.
> >
> > Signed-off-by: Sander Vanheule <sander@xxxxxxxxxxxxx>
> 
> That sounds complicated.
> 
> Sounds like something the IRQ maintainer (Marc Z) should
> have a quick look at.

This is pretty odd indeed. There seem to be a direct mapping between
the GPIOs and the CPU it interrupts (or at least that's what the code
seem to express). However, I don't see a direct relation between the
CPUs and the chained interrupt. It isn't even clear if this interrupt
itself is per-CPU.

So this begs a few questions:

- is the affinity actually affecting the target CPU? or is it
  affecting the target mux?

- how is the affinity of the mux interrupt actually enforced?

	M.

-- 
Without deviation from the norm, progress is not possible.