Bart, side note: I can't see your for-current in Linux Next for a few days, is everything okay? On Wed, Mar 9, 2022 at 1:47 AM Kris Bahnsen <kris@xxxxxxxxxxxxxx> wrote: > > From: Mark Featherston <mark@xxxxxxxxxxxxxx> > > This works around an issue with the hardware where both OE and > DAT are exposed in the same register. If both are updated > simultaneously, the harware makes no guarantees that OE or DAT hardware the OE > will actually change in any given order and may result in a > glitch of a few ns on a GPIO pin when changing direction and value > in a single write. > > Setting direction to input now only affects OE bit. Setting the OE bit > direction to output updates DAT first, then OE. > > Fixes: 9c6686322d74 ("gpio: add Technologic I2C-FPGA gpio support") > There must be no blank lines in the tag block. > Signed-off-by: Mark Featherston <mark@xxxxxxxxxxxxxx> > Signed-off-by: Kris Bahnsen <kris@xxxxxxxxxxxxxx> ... > + * Copyright (C) 2015-2018 Technologic Systems Not sure it's a valid change for a simple fix. ... > - /* > - * This will clear the output enable bit, the other bits are > - * dontcare when this is cleared > + /* Only clear the OE bit here, requires a RMW. Prevents potential issue > + * with OE and data getting to the physical pin at different times. > */ Keep the proper style for multi-line comments. ... > + /* If changing from an input to an output, we need to first set the > + * proper data bit to what is requested and then set OE bit. This the OE bit > + * prevents a glitch that can occur on the IO line > + */ Keep the proper style. -- With Best Regards, Andy Shevchenko