Re: RFC: pinctrl: baytrail: Need to fixup mux setting due to broken BIOS/DSDT

[Hans de Goede <hdegoede@xxxxxxxxxx>]

Hi,

On 1/16/22 22:11, Andy Shevchenko wrote:
> On Sat, Jan 15, 2022 at 6:45 PM Hans de Goede <hdegoede@xxxxxxxxxx> wrote:
>>
>> Hi Andy, Mika,
>>
>> For one of the x86 Android tablets with broken DSDTs which I'm working on
>> I need to change the mux value of pin 6 of SUS aka INT33FC:02 from 0 to 1,
>> this changes it from a normal GPIO to outputting the PMC's 32KHz clk.
>> This is needed for the jack-detection in the audio codec which needs an
>> external 32KHz clock to work and that is connected to pin 6 of SUS.
>>
>> On the Windows version of the same tablet (which uses slightly different
>> hardware, e.g. there is an embedded controller on the board which the
>> Android version lacks) there is an ACPI call to toggle the mux, since
>> the firmware does not set it for us.
>>
>> So the x86-android-tablets.c code for working around all the firmware
>> challenges on these devices will need a way to toggle the mux and
>> directly poking it itself is a bad idea because of the need
>> to serialize all accesses to the GPIO islands on byt, see:
>>
>> 39ce8150a079 ("pinctrl: baytrail: Serialize all register access")
>>
>> So I see 2 possible options:
>>
>> 1. Add a pingroup for this pin in drivers/pinctrl/intel/pinctrl-baytrail.c
>> and then mimick the pwm0 pinconf setting code from
>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c in x86-android-tablets.c
>> This seems the cleanest, but I'm leaning a bit towards:
> 
> If you meant
> https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/i915/display/intel_dsi_vbt.c#L858
> this is definitely the way to go.

Ok, I already figured as much, thank you for your input.

Regards,

Hans