On Fri, Jan 07, 2022 at 06:41:30PM +0200, Andy Shevchenko wrote: > On Fri, Jan 07, 2022 at 03:23:43PM +0100, Hans de Goede wrote: ... > > +static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 value) > > +{ > > + void __iomem *reg; > > + int i, j; > > + > > + if (!(value & (BYT_TRIG_POS | BYT_TRIG_NEG))) { > > + dev_warn(vg->dev, > > + FW_BUG "pin %i: direct_irq_en set without trigger, clearing\n", pin); > > + return false; > > + } > > + > > + reg = vg->communities->pad_regs + BYT_DIRECT_IRQ_REG; > > > + for (i = 0; i < 16; i += 4) { > > + value = readl(reg + i); > > + for (j = 0; j < 4; j++) { > > + if (((value >> j * 8) & 0xff) == pin) { > > Can it be like > > u32 direct_irq[16]; > void __iomem *reg; > void *match; > > > memcpy_fromio(...); > match = memchr(...); > if (match) > dev_dbg(); > else > dev_warn(); > > return !!match; > > ? > > > + dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (APIC %d)\n", > > + pin, i + j, 0x43 + i + j); Why 0x43 is hard coded? > > + return true; > > + } > > + } > > + } > > + > > + dev_warn(vg->dev, > > + FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin); > > + return false; > > +} -- With Best Regards, Andy Shevchenko