Re: [PATCH v2 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver

[Emil Renner Berthing <kernel@xxxxxxxx>]

On Fri, 22 Oct 2021 at 15:39, Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote:
> On Fri, Oct 22, 2021 at 4:35 PM Emil Renner Berthing <kernel@xxxxxxxx> wrote:
> > On Fri, 22 Oct 2021 at 14:56, Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote:
> > > On Thu, Oct 21, 2021 at 8:43 PM Emil Renner Berthing <kernel@xxxxxxxx> wrote:
>
> ...
>
> > > Why all these ugly % 32 against constants?
> >
> > Because the JH7100_RST_ values goes higher than 31. There is a
> > BIT_MASK macro, but that does % BITS_PER_LONG and this is a 64bit
> > machine.
>
> And? It's exactly what you have to use!

So you want me to use an unsigned long array or DECLARE_BITMAP and
juggle two different index and bit offsets?
Also is there a macro for handling that we'd then need 4 commas on
32bit COMPILE_TEST and 2 commas on 64bit?
If you have some other way in mind you'll have to be a lot more explicit again.

The point of the jh7100_reset_asserted array is that it exactly
mirrors the values of the status registers when the lines are
asserted. Maybe writing it like this would be more explicit:

static const u32 jh7100_reset_asserted[4] = {
        /* STATUS0 register */
        BIT(JH7100_RST_U74 % 32) |
        BIT(JH7100_RST_VP6_DRESET % 32) |
        BIT(JH7100_RST_VP6_BRESET % 32),
        /* STATUS1 register */
        BIT(JH7100_RST_HIFI4_DRESET % 32) |
        BIT(JH7100_RST_HIFI4_BRESET % 32),
        /* STATUS2 register */
        BIT(JH7100_RST_E24 % 32),
        /* STATUS3 register */
        0,
};