On Tue, 2021-02-02 at 12:42 +0100, Bartosz Golaszewski wrote: > On Thu, Jan 28, 2021 at 4:36 PM Alban Bedel <alban.bedel@xxxxxxxx> > wrote: > > From a quick glance at various datasheet the PCAL6524 seems to be > > the > > only chip in this familly that support setting the drive mode of > > single pins. Other chips either don't support it at all, or can > > only > > set the drive mode of whole banks, which doesn't map to the GPIO > > API. > > > > Add a new flag, PCAL6524, to mark chips that have the extra > > registers > > needed for this feature. Then mark the needed register banks as > > readable and writable, here we don't set OUT_CONF as writable, > > although it is, as we only need to read it. Finally add a function > > that configure the OUT_INDCONF register when the GPIO API set the > > drive mode of the pins. > > > > Signed-off-by: Alban Bedel <alban.bedel@xxxxxxxx> > > --- > > drivers/gpio/gpio-pca953x.c | 64 > > +++++++++++++++++++++++++++++++++++-- > > 1 file changed, 61 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio- > > pca953x.c > > index 825b362eb4b7..db0b3dab1490 100644 > > --- a/drivers/gpio/gpio-pca953x.c > > +++ b/drivers/gpio/gpio-pca953x.c > > @@ -64,6 +64,8 @@ > > #define PCA_INT BIT(8) > > #define PCA_PCAL BIT(9) > > #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) > > +#define PCAL6524 BIT(10) > > Maybe call it PCAL6524_TYPE for consistency with the ones below? This is a flag that, like the above ones, indicate the existence of registers, the types found under indicate a different register layout. Misusing the naming convention would probably be confusing. A generic name that don't reference the part type (PCA_???) would perhaps be better but as I couldn't find any other part with these registers I left it at that for now. > > + > > No need for this newline. I'll fix all the style issues you pointed out. Alban
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