Re: [PATCH v3 1/4] pinctrl: amd: fix incorrect way to disable debounce filter

[Hans de Goede <hdegoede@xxxxxxxxxx>]

Hi,

On 11/6/20 12:19 AM, Coiby Xu wrote:
> The correct way to disable debounce filter is to clear bit 5 and 6
> of the register.
> 
> Cc: Hans de Goede <hdegoede@xxxxxxxxxx>
> Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@xxxxxxxxxx/
> Signed-off-by: Coiby Xu <coiby.xu@xxxxxxxxx>

Thanks, patch looks good to me:

Reviewed-by: Hans de Goede <hdegoede@xxxxxxxxxx>

Regards,

Hans

> ---
>  drivers/pinctrl/pinctrl-amd.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
> index 9a760f5cd7ed..d6b2b4bd337c 100644
> --- a/drivers/pinctrl/pinctrl-amd.c
> +++ b/drivers/pinctrl/pinctrl-amd.c
> @@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
>  			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
>  			pin_reg |= BIT(DB_TMR_LARGE_OFF);
>  		} else {
> -			pin_reg &= ~DB_CNTRl_MASK;
> +			pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
>  			ret = -EINVAL;
>  		}
>  	} else {
>  		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
>  		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
>  		pin_reg &= ~DB_TMR_OUT_MASK;
> -		pin_reg &= ~DB_CNTRl_MASK;
> +		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
>  	}
>  	writel(pin_reg, gpio_dev->base + offset * 4);
>  	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
>